Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Abstract: An ultra-low power (ULP), power gated static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates in sub-threshold voltage ranges from 300mV to 500mV. The proposed SRAM has tendency to operate in low supply voltages with high static and dynamic noise margins. The IoT application involves battery enabled low leakage memory architecture in subthreshold regime which has low power consumption. Therefore, to improve power consumption along with better cell stability, a power gated 10T SRAM is presented. The proposed cell uses a power gated p-MOS transistor to reduce the leakage power or static power in standby mode. Moreover, due to the schmitt triggering and read decoupling of 10T SRAM the static and dynamic behavior in read, write and standby mode has shown enhanced tolerance at different process, voltage and temperature (PVT) conditions. The proposed SRAM shows better results in terms of leakage power, read static noise margin (RSNM), write static noise margin (WSNM), write-ability or write trip point (WTP), read-write energy and dynamic read margin (DRM). Further, these parameters are observed at 8-Kilo bit (Kb) and compared with already existing SRAM architectures. It is observed that the leakage power is reduced by 1/81×, 1/75× of the conventional 6T (C6T) SRAM and read decoupled 8T (RD8T) SRAM, respectively at 300mV VDD. On the contrary, RSNM, WSNM, WTP and DRM values are improved by 3×, 2×, 11.11% and 31.8% as compared to C6T SRAM, respectively. Similarly, proposed 10T has 1.48×, 25% and 9.75% better RSNM, WSNM and WTP values as compared to RD8T SRAM, respectively at 300mV VDD.